I have uploaded my whole Project vivado file on Github. to access that click here.

Final testing of the video 

 

 Image flow

In this Image the flow of the image is shown along the process.

It starts with the the web cam where the image is capured and then the image is converted to the digital image. 

after that that digital image is transfered to FPGA board with the help of usb cable. the digital image goes to pre-production block in which the digital image is broken bown for further process. 

Then the data goes to the Pynq processor and then as per the requirement the data is stored or processed or send to other area the hardware.

After that the data is compiled agian so that it can be send to other digital devices.

At the end the image is send to dispay with the help HDMI cable to show the final processed image. 

 Errors in rebuilding the Pynq base pipeline

When I was trying to rebuild the pipeline I came across a lot of errors. And I solved them in small steps .

The first error was while redevloping the IPs from the pynq/board/ip/hls.

In the lab2 the bat file was used to redevelop but that did not work for my system. So after doing research and trying other ways to redevelop as i tried with the help of vivado hls, vitis hls and other ways to run tcl files but later I found that I need Xilinx Vitis 2020.1, not 2020.2. Based on the refrence of form.

After reinstalling the softwares I Still got this error. as shiown in the image bellow.

after that from this error I though it would be easy if I can comment out the testing phase of the tcl file so it will built the IP but want test it. and on trying that it seemed to work but  then the IPs were not built.

So, later on I found that their is a patch needed to be used to solve the issue from the link.

So After aplying the patch I was still having the error. So I went to the pynq support and rise the query.

the next day I got the reply from mario as that I the file was located at the different location.

So then I cleared and cheeked all the locations of the files and recloned the file.but still was having the same issue and the I reached out to the support again. And this time they replied saying that the pynq file version and the vivado verson that i was working on did not match.

So, now I tried to change the pynq file version to pynq v2.6. and run the tcl fil again and this time I was succesful and after that I was able to rebuilt the base pipeline.

 

References

References

https://github.com/wbrueckner/cv2pynq    ----similar project

https://www.hackster.io/adam-taylor/fpga-based-edge-detection-using-hls-192ad2    —- adams edge detection

https://github.com/Pieter-Berteloot/PYNQ_Projects/blob/master/Report.pdf    --- video acceleration